1. Field of the Invention
The present invention relates to a lateral type power MOS (Metal Oxide Semiconductor) transistor and a fabrication method thereof. In particular, the present invention relates to a lateral type power MOS transistor using an SOI (Silicon On Insulator) substrate and a fabrication thereof.
2. Description of the Prior Art
A conventional lateral type power MOS transistor 100 using an SOI substrate will be described with reference to FIG. 1. The SOI substrate 20 includes a buried silicon oxide film (SiO2) 2 formed as a buried insulator film on a support substrate 1 of a semiconductor material or an electrically conductive material and an Nxe2x88x92 type semiconductor layer 3 formed on the buried silicon oxide film 2. In the semiconductor layer 3, a shallow N type well region 4, which does not reach the buried silicon oxide film 2, and a deep P type base region 5, which reaches the buried silicon oxide film 2, are formed in separate positions of the semiconductor layer 3, respectively. An N+ type drain region 6 is formed in the N type well region 4. In the base region 5, an N+ type source region 7 is formed separately from a PN junction between the semiconductor layer 3 and the base region 5 by a predetermined distance to hold a predetermined channel length. A gate insulating film 8 of thin silicon oxide is formed on a portion of the base region 5 between the semiconductor layer 3 and the source region 7, and a gate electrode 9 of polysilicon is formed on the gate insulating film 8. A field oxide film 10 of thick silicon oxide is formed on a portion of the N type well region 4 between the semiconductor layer 3 and the drain region 6. A drain electrode 12 is formed on the drain region 6 such that the drain electrode is electrically in contact with the drain region 6. A source electrode 13 is formed on the base region 5 and the source region 7 such that the source electrode is electrically in contact with the base region 5 and the source region 7. The drain electrode 12 and the source electrode 13 are electrically separated from the gate electrode 9 by an inter-layer insulating film (SiO2) 11 covering the gate electrode 9.
A fabrication method of the MOS transistor 100 having the above-described construction will be described with reference to FIG. 1 and FIG. 2A to FIG. 2C.
In a first step, the SOI substrate 20 is prepared, in which the Nxe2x88x92 type semiconductor layer 3 is formed on the SOI substrate 1 with the buried silicon oxide film 2 interposed therebetween. In the first step, after the field oxide film 10 is formed on the semiconductor layer 3 by LOCOS (Local Oxidation of Silicon), a thin silicon oxide film 21 for ion injection is formed by thermal oxidation. And then phosphor (P) ion is selectively injected into the upper surface portion of the semiconductor layer 3 by using a photolithography technique with a resist pattern 22 used as a mask. After the resist pattern 22 is removed, the N type well region 4 is formed by thermal diffusion of phosphor. A result of the first step is shown in FIG. 2A.
In a second step, the silicon oxide film 21 is removed by wet etching and then the gate insulating film 8 is formed by thermal oxidation. A polysilicon film is grown on the gate insulating film 8 by CVD (Chemical Vapor Deposition) and the gate electrode 9 is formed by removing unnecessary portion of the polysilicon film by dry etching with using a resist pattern as a mask. Thereafter, boron (B) ion is selectively injected into the upper surface portion of the semiconductor layer 3 by photolithography with using the gate electrode 9 and a resist pattern 23 as a mask. After the resist pattern 23 is removed, the deep P type base region 5 reaching the buried silicon oxide film 2 is formed by thermal diffusion of boron. A result of the second step is shown in FIG. 2B.
In a third step, arsenic (As) ion is selectively injected into the upper surfaces of the N type well region 4 and the base region 5 by photolithography with using the gate electrode 9 and a resist pattern 24 as a mask. After the resist pattern 24 is removed, the drain region 6 and the source region 7 are formed in the surface portions of the N type well region 4 and the base region 5, respectively, by thermal diffusion of arsenic. A result of the second step is shown in FIG. 2C.
In a fourth step, a surface of the wafer obtained by the third step is covered by the interlayer insulating film 11 by using CVD. After contact windows are formed in the interlayer insulating film 11 and the gate insulating film 8 such that surfaces of the base region 5, the drain region 6 and the source region 7 are exposed, an aluminum film is formed thereon by sputtering. And then the drain electrode 12, which is electrically in contact with the drain region 6 and the source electrode 13, which is electrically in contact with the base region 5 and the source region 7, are formed by selectively removing the aluminum film with using photolithography and dry etching. A result of the fourth step is shown in FIG. 1.
In forming the base region 5 and the source region 7 of the conventional lateral type power MOS transistor 100 mentioned above, the base region 5 reaching the buried silicon oxide film 2 is formed by ion injection and thermal diffusion with using the gate electrode 9 as the mask. Therefore, the base region 5 becomes laterally widened substantially and the channel length of the channel layer formed in the base region 5 between the source region 7 and the semiconductor layer 3 is elongated. Consequently, there is a problem that the on-resistance is increased. Further, in order to realize a high frequency signal control of the MOS transistor, it is preferable to reduce an output capacitance of the transistor.
An object of the present invention is to provide a lateral type power MOS transistor having reduced on-resistance and reduced output capacitance and a fabrication method of the same MOS transistor.
The lateral type power MOS transistor according to the present invention, which includes a support substrate formed of an electrically conductive material including a semiconductor material, a buried insulating film, and a semiconductor layer of one conductivity type formed on the buried insulating film. A groove having a generally U-shape cross section is formed in the semiconductor layer, and a gate electrode is formed in the groove with a gate insulating film interposed therebetween. A base region of the other conductivity type having a depth substantially the same as that of the groove is formed in a surface portion of the semiconductor layer adjacent to a side wall of the groove on one side of the groove. A high impurity density source region of the one conductivity type is formed in a surface portion of the base region adjacent to the side wall of the groove. A low impurity density region of the other conductivity type having impurity density lower than that of the base region is formed between the base region and the buried insulating film and a high impurity density drain region of the one conductivity type is formed in the surface layer of the semiconductor layer on the other side of the groove. The present invention is featured by that a PN junction of the low impurity density region of the other conductivity type and the semiconductor layer is formed in substantially coplanar with the side wall of the groove on the side of the base region.
A fabrication method for fabricating this lateral type power MOS transistor includes following steps:
preparing an SOI substrate including an electrically conductive support substrate, a buried insulating film formed therein and a semiconductor layer of one conductivity type formed on the buried insulating film;
forming a low impurity density well region of the other conductivity type reaching the buried insulating film in the semiconductor layer;
forming a groove having a generally U-shape cross section and having depth smaller than that of the well region in the semiconductor layer adjacent to a side wall of the well region and a gate electrode in the groove with a gate insulating film interposed therebetween;
forming a base region of the other conductivity type having substantially the same depth as that of the groove in a surface layer of the well region of the other conductivity type adjacent to the side wall of the groove; and
forming a high impurity density source region of the one conductivity type in a surface portion of the base region adjacent to the side wall of the groove and a high impurity density drain region of the one conductivity type in the surface layer of the semiconductor layer on the other side of the groove.